1. Technical Field
The present invention relates to a method for manufacturing a memory device, and more particularly, to a method for manufacturing a memory device with reduced sub-threshold voltage issues.
2. Description of the Related Art
Small sizes, faster speed performances and larger memory capacities are important characteristics for dynamic random access memories (DRAMs). Typically, standard DRAM cells include a transistor and a capacitor. Since the capacity of standard DRAMs has reached 256 MB and up to 512 MB, the size of memory cells and transistors has shrunk to meet demands for high integration, higher memory capacity and higher operating speeds.
A DRAM is an important semiconductor device in the information and electronics industry. Most DRAMs have one access transistor and one storage capacitor in one DRAM cell. With increased integration, however, 3-D capacitors, such as deep trench capacitors, have become necessary. Generally the storage capacitor is formed within a deep trench etched into a semiconductor substrate. The storage capacitor is accessed using an access transistor which allows charges to be stored in the storage capacitor or retrieves charges from the storage capacitor depending on whether the desired action is a read or write function.
FIG. 1 is a conventional dynamic random access memory (DRAM) cell 50 layout. An access transistor 14 includes a gate conductor (i.e. wordline) 12, source region 16, a drain region 18, and a nitride cap (NIT) 30 which are bordered by insulation spacers 32. Deep trench capacitors 10 are disposed under and passing the gate conductor 12 and embedded into a substrate 60. The source region 16 is electrically coupled to a bit line contact 20 which connects to bit lines (not shown) for reading and writing to the storage node 15 through the access transistors 14, and the drain region 18 is electrically coupled to a buried strap outdiffusion 22 of a storage node 15 of the trench capacitors 10 through diffusion regions 27 formed by subjecting the drain region 18 to a rapid thermal process (RTP). Access transistors 14 are activated by the gate conductor 12. The entire structure is covered with an insulator 28 such as boron phosphorous silicate glass (BPSG) which includes an underlying insulator layer 34. The storage node 15 is isolated by a dielectric collar 26. A shallow trench isolation (STI) 24 is provided over the storage nodes 15 to electrically isolate the gate conductor 12 formed above the storage nodes 15.
When voltage is applied to the gate conductor 12, a channel below the gate conductor 12 is conducted and allows current to flow between a source region 16 and a drain region 18 and into or out of the storage node 15. The gate conductor 12 is preferably spaced across the smallest possible distance to conserve layout area. As integration of semiconductor devices increases, the transistors therein, are being gradually scaled down. As a result, the channel length L of the transistors is being reduced, and thus the distance between the source region 16 and the diffusion regions 27 is also being reduced, which may cause a short channel effect involving punch-through, and degradation of sub-threshold voltage (sub-vt).
Further, in the convention process for fabricating DRAMs, the rapid thermal process for forming diffusion regions 27 thereof, has a process temperature as high as possible, in order to ensure that the drain region 18 can be electrically coupled to the buried strap outdiffusion 22 through the diffusion regions 27. Accordingly, the high process temperature of the rapid thermal process increases the impurity concentration of the diffusion regions 27, thereby increasing the risk of short channel effect.
In order to avoid short channel effect, a tilted ion implant (such as a halo implant) is performed to the substrate 60 to surround the source region 16, which prevents the occurrence of the short channel effect, or leakage current, and reduces problems occurring from the sub-threshold voltage (sub-vt) issue. For a halo implant, the implantation dose is increased in order to suppress the short channel effect. A high halo implantation dose, however, degrades the electrical contact between the source region 16 and the bit line contact and reduces the data retention time of DRAMs.
Therefore, a novel method for fabrication of a DRAM which overcomes the above problems is desired.